Performance Enhancement of Cisc Microcontroller

Abstract

Increase in the speed of the system always demands for a major alteration on the existing system, which result in overall cost of the implementation of a system. Generally, CISC controllers are used for control operations, which have large number of instruction sets and take a large amount for processing due to its multiple sizes. For very high speed of controlling these controllers may fail to operate properly. The alternate solution is the RISC controllers, which are considerably faster than the normal CISC controllers. But these controllers have got various limitations as less instruction operations, complex register operation, costlier than the CISC controller etc. The only solution to this problem is the enhancement to the operational speed of a CISC controller, by enhancing the overall controller operation. Additionally, today�s controller doesn�t support the floating-point operation for signal processing. The enhancement of existing CISC controller by pipelining the overall operational flow of a CISC microcontroller and it includes the enhancement of UART. This research work is to be implemented using VHDL language and simulated using Active-HDL tool for functional verification.