Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance

Abstract

Data compression is one of the major fields of research in the present world. In this regard image compression is also having its own significance, so many algorithms for DFT, DCT, DWT, etc. have been developed and among them DWT is most likely used there are two plans are existing for generating 2-DWT and are lifting and flipping plans. The above two plans architecture are having its own fixed scaling constants, multipliers and adders. In my project work I am proposing a lifting plan and flipping plan such that the modification is done in its internal architecture of S.M.B.Multiplier and radix-4 booth multiplier with replacing adder in it with spanning tree parallel prefix adder. This modification has improved Power Delay Product (PDP) by 7% in lifting plan and 5% in flipping plan.